3DML: Open-Source

AutoDNNChip [github]

An automated DNN chip generator for both FPGA and ASIC DNN chip implementation.

  • A Chip Predictor that can accurately and efficiently predict a DNN accelerator’s energy, throughput, latency, and area based on the DNN model parameters, hardware configuration, technology-based IPs, and platform constraints.

  • A Chip Builder automatically explores the design space of DNN chips and optimizes chip design via the Chip Predictor, and then generate synthesizable RTL code with optimized dataflows to achieve the target design metrics.

More tools coming soon ...